syntax - VHDL prog to implement 8to1 mux using 4to1 (structural modelling) -
i student , have started learning vhdl. need point me in right direction. have done far:
library ieee; use ieee.std_logic_1164.all; entity mux81 port( : in std_logic_vector(7 downto 0); s : in std_logic_vector(2 downto 0); z : out std_logic); end mux81; architecture struc of mux81 signal z1,z2:std_logic; component mux41 port(a,b,c,d,s0,s1:in std_logic;q:out std_logic); end component; component mux21 port(m,n,s2:in std_logic;o:out std_logic); end component; m1,m2:mux41 use entity work.mux41(struc1); m3:mux21 use entity work.mux21(arc); signal z1,z2: std_logic; begin m1 : mux41 port map(a(0),a(1),a(2),a(3),s(0),s(1),z1); m2 : mux41 port map(a(4),a(5),a(6),a(7),s(0),s(1),z2); m3 : mux21 port map(z1,z2,s(2),o); end struc; library ieee; use ieee.std_logic_1164.all; entity mux41 port( : in std_logic_vector(3 downto 0); s : in std_logic_vector(1 downto 0); z : out std_logic); end mux41; architecture struc1 of mux41 component and3 (a,b,c : in std_logic;d : out std_logic); end component; component or4 (a,b,c,d : in std_logic;e : out std_logic); end component; a1,a2,a3,a4:and3 use entity work.and3(arc3); or1:or4 use entity work.or4(arc2); signal s1,s2,s3,s4 : std_logic; begin a1 : and3 port map(a(0),not s(0),not s(1),s1); a2 : and3 port map(a(1),not s(0),s(1),s2); a3 : and3 port map(a(2),s(0),not s(1),s3); a4 : and3 port map(a(3),s(0),s(1),s4); or1 : or4 port map (s1,s2,s3,s4,z); end struc1; library ieee; use ieee.std_logic_1164.all; entity mux21 port(a,b,s : in bit; c : out bit); end mux21; architecture arc of mux21 signal o1,o2:std_logic; component and3 (a,b,c : in std_logic;d : out std_logic); end component; component or2 (a,b : in std_logic;c : out std_logic); end component; a5,a6:and3 use entity work.and3(arc3); o1:or2 use entity work.or2(arc1); begin a5 : and3 port map(z1,not s2,o1); a6 : and3 port map(z2,s2,o2); o1 : or2 port map(o1,o2,o); end arc; library ieee; use ieee.std_logic_1164.all; entity or2 port(a,b : in bit; c : out bit); end or2; architecture arc1 of or2 begin c<=a or b; end arc1; library ieee; use ieee.std_logic_1164.all; entity or4 port(a,b,c,d : in bit; e : out bit); end or4; architecture arc2 of or4 begin e<=a or b or c or d; end arc2; library ieee; use ieee.std_logic_1164.all; entity and3 port(a,b,c : in bit; d : out bit); end and3; architecture arc3 of and3 begin d<=a , b , c; end arc3; error log:
# compile... # file: c:\users\divyanshu\downloads\hdl\div\mux\src\try.vhd # compile entity "mux81" # entity `mux81' has been skipped - no difference detected. # compile architecture "struc" of entity "mux81" # error: elab1_0021: try.vhd : (18, 1): types not match port "a". # error: elab1_0011: try.vhd : (18, 0): port "s" on entity "mux41" not on component declaration. # error: elab1_0030: try.vhd : (18, 0): port "b" on component "mux41" not on entity "mux41". # error: elab1_0030: try.vhd : (18, 0): port "c" on component "mux41" not on entity "mux41". # error: elab1_0030: try.vhd : (18, 0): port "d" on component "mux41" not on entity "mux41". # error: elab1_0030: try.vhd : (18, 0): port "s0" on component "mux41" not on entity "mux41". # error: elab1_0030: try.vhd : (18, 0): port "s1" on component "mux41" not on entity "mux41". # error: elab1_0030: try.vhd : (18, 0): port "q" on component "mux41" not on entity "mux41". # error: comp96_0122: try.vhd : (21, 1): symbol "z1" has been declared in region. # error: comp96_0122: try.vhd : (21, 1): symbol "z2" has been declared in region. # error: comp96_0078: try.vhd : (25, 32): unknown identifier "o". # error: comp96_0133: try.vhd : (25, 32): cannot find object declaration. # error: comp96_0104: try.vhd : (25, 32): undefined type of expression. # compile entity "mux41" # entity `mux41' has been skipped - no difference detected. # compile architecture "struc1" of entity "mux41" # error: comp96_0019: try.vhd : (39, 1): keyword "end" expected. # error: comp96_0018: try.vhd : (40, 14): identifier expected. # error: comp96_0019: try.vhd : (42, 1): keyword "end" expected. # error: comp96_0018: try.vhd : (43, 14): identifier expected. # compile entity "mux21" # entity `mux21' has been skipped - no difference detected. # compile architecture "arc" of entity "mux21" # error: comp96_0019: try.vhd : (67, 1): keyword "end" expected. # error: comp96_0018: try.vhd : (68, 14): identifier expected. # error: comp96_0019: try.vhd : (70, 1): keyword "end" expected. # error: comp96_0018: try.vhd : (71, 14): identifier expected. # compile entity "or2" # entity `or2' has been skipped - no difference detected. # compile architecture "arc1" of entity "or2" # compile entity "or4" # entity `or4' has been skipped - no difference detected. # compile architecture "arc2" of entity "or4" # compile entity "and3" # entity `and3' has been skipped - no difference detected. # compile architecture "arc3" of entity "and3" # compile failure 21 errors 0 warnings analysis time : 0.4 [s] i know errors basic first project on vhdl myself. thanx in advance.
you have component declaration
component mux41 port(a,b,c,d,s0,s1:in std_logic;q:out std_logic); and entity declaration
entity mux41 port( : in std_logic_vector(3 downto 0); s : in std_logic_vector(1 downto 0); z : out std_logic); end mux41; these different. , error messages tell wrong.
error: elab1_0021: try.vhd : (18, 1): types not match port "a". error: elab1_0011: try.vhd : (18, 0): port "s" on entity "mux41" not on component declaration. error: elab1_0030: try.vhd : (18, 0): port "b" on component "mux41" not on entity "mux41". error: elab1_0030: try.vhd : (18, 0): port "c" on component "mux41" not on entity "mux41".` indeed port std_logic in one, , std_logic_vector in other : message says, these not match. , entity has port "s" while component not. , on...
fixing them might involve writing new entity matches component, or editing component declaration , port maps match entity have.
and morten , says, catch basic errors in simulation... if can't access modelsim, free xilinx tools contain decent simulator (isim) or there open-source tool ghdl.
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